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W99686F Data Sheet SYSTEM CAMERA DEVICE
Table of Contents1. 2. 3. GENERAL DESCRIPTION ......................................................................................................... 2 FEATURES ................................................................................................................................. 2 APPLICATION ............................................................................................................................ 6 3.1 3.2 3.3 4. 4.1 4.2 5. 5.1 5.2 System Overview ............................................................................................................ 6 Host Interface ................................................................................................................. 6 Camera Implementation ................................................................................................. 9 W99686F Pin Definition (108 balls, LFBGA Package) ................................................. 10 W99686F-108b Pin Assignment - (Top View) ............................................................. 14 Absolute Maximum Ratings .......................................................................................... 17 DC Characteristics........................................................................................................ 17
5.2.1 5.2.2 5.2.3 5.2.4 RESET AC Characteristics.............................................................................................18 Video Input AC Characteristics.......................................................................................18 Host Interface: CF-IDE Slave (Memory Bus) AC Characteristics ...................................19 LCD Interface AC Characteristics...................................................................................20
PIN DESCRIPTION................................................................................................................... 10
ELECTRICAL CHARACTERISTICS......................................................................................... 17
6. 7.
PACKAGE DIMENSION ........................................................................................................... 21 REVISION HISTORY ................................................................................................................ 22
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Publication Release Date:April 13, 2005 Revision A7
W99686F
1. GENERAL DESCRIPTION
W99686F is a high performance and highly-integrated system camera device that it can preview, capture, compress, store, and display the digital still images or playback a short period of live video. This chip provide 8 or 16 Bits Host interface and easy for base band chip( Host ) to develop Camera function through Command set protocol that allow the development of products without knowing any W99686F chip programming. W99686F Built-in 8-bit 8032 compatible C with internal 16KB program RAM and 4K data RAM. Program can be down load from Host bus interface. This chip also Built-in 8M byte frame buffer for real-time video clip (MJPG) and burst snapshot. Support CCIR-656 8-bit YUV CMOS or CCD capture sensor interface. W99686F Support up to dual LCD Panels interface with MCU type interface. Support TFT-LCD, CSTN-LCD, STN-LCD Panel Types, If camera function is active, The host CPU can use W99686F as the bridge (display controller) to LCM. And it can provide multiple display buffers. If camera function is disabled, the host CPU can use bypass mode to control the LCM directly for maximum power saving. W99686F Support dual video pipes and double buffering for real-time motion JPEG, Support smooth digital zoom of video pipes, different kinds of raw data formats for display, some popular image color effects (Black & White, Sepia, Negative, Solarize or Oil Painting), Video Rotation / Mirror / Flip for capture and playback, Sticker maker, Comic Photo maker and smart frame rate control.
2. FEATURES
General * * * * 0.18um logic process Core 1.8V I/O 2.6V - 3.6V Power consumption - - * * * * * * * < 23mA for 160x120 @ 15 fps, 2.8V preview mode < 35mA for 160x120 @ 30fps, 2.8V preview mode
Support power-down mode Support LCD bypass mode Support GPIO pins for flash light control or else Built-in smart processor to allow the development of products without knowing any W99686 chip programming. Minimum product design cycle time for fast time-to-market Built-in 8-bit 8032 compatible uC with internal 16KB program RAM and 4K data RAM Program can be down load from host interface. Built-in 8M bytes frame buffer for real-time video clip (M-JPEG) and burst snapshot.
* Support VGA/1.3M/2.1M image resolution
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W99686F
Sensor Interface * Support CCIR-656 8-bit YUV CMOS or CCD capture interface * * * * * * * * * * * * CMOS Type Omni-Vision OV9640 Omni-Vision OV7645/OV7648 CI-Sensor CISVV11 Toshiba TCM8210 Sharp PixelPlus PO1030K Samsung, Micron, Fujitsu...Etc. CCD Type SANYO IGT99267/IGT99268 Etc. Supports fast serial interface to program image sensor.
Host Interface * 8/16 bits parallel Bus (Indirect access) * Easy for base band chip( Host ) to develop Camera function through Command set protocol. LCD Display Interface * Support up to dual LCD Panels interface * Supports MCU type interface LCD module * Supports 8/16/18-bit display data output to LCD Penal * Support 4 kinds of display data format out to LCD Penal - - - - 256 colors (RGB-332) 4096 colors (RGB-444) 64k colors (RGB-565) 256k colors (RGB-666)
* Support LCD interface bypass mode * Support TFT-LCD, CSTN-LCD, STN-LCD Panel Types * * If camera function is active, the host CPU can use W99686F as the bridge (display controller) to LCM. And it can provide multiple display buffers. If camera function is disabled, the host CPU can use bypass mode to control the LCM directly for maximum power saving.
JPEG CODEC for Image Compression and Decompression * Fully compliant with ISO/IEC 10918-1 international JPEG standard * JPEG compression and decompression for still images * Real-time motion JPEG (M-JPEG) compression with advanced bit rate control for live video
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W99686F
* JPEG baseline sequential mode in interleaved scan YcbCr(4:2:2) or YcbCr(4:2:0) format * Support adjustable quantization table for different compression ratio * Support smooth digital zoom * Support JPEG re-sizing and re-encoding Operation Modes * * * * * * * * Preview ModeFrame rate up to 30 fps Single Snapshot Mode Burst Snapshot Mode - - Support up to 10 frames burst snapshot at 1/30 sec interval About 100 seconds recording time with 4M bytes vedio buffer at 320x240 size @ 15 fps Movie Mode (Motion JPEG) Playback Mode Comic Photo Mode Transfer Mode Still Image Size - - - - - - - - * - - - 2048 x 1536(QXGA) 1600 x 1200(UXGA) 1280 x 1024(SXGA) 1280 x 960 (SXGA) 640 x 480 (VGA) 320 x 240 (QVGA) 160 x 120 (QQVGA) Subject to change by request 320 x 240 (QVGA) 160 x 120 (QQVGA) Subject to change by request
Video Clip Size
Video Display Function * Support high-color / OSD Video overlay function * Support graphics/video blending * Support image Rotation / Flip / Mirror - - - - - Left 90 degree rotation Right 90 degree rotation 180 degree rotation Horizontal mirror Vertical flip
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W99686F
* Support image color effects - - - - - Normal Black & white Sepia Negative Solarize / oil painting
* Support image sticker maker * Support imprint of message photo * Support comic photo maker * Support OSD Video overlay function * * * * * Support dual video pipes and double buffering for real-time Motion JPEG Support arbitrary N/M (=[0..255]) scaling-down of video pipes Support different kinds of raw data formats for display Support some popular image color effects Support smart frame rate control
USB Interface * Compliant with USB Spec. Rev. 1.1 specification * Supports three USB pipes including: - - - Control pipe Bulk-in pipe Bulk-out pipe
Power Management * Advanced power management including: - - - Power-down mode Stand-by mode Operating mode
Package: * W99686F/ BGA 108-Balls package (8mm x 8mm)
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Publication Release Date: April 13, 2005 Revision A7
W99686F
3. APPLICATION
3.1 System Overview
Sensor
W99686F
(single chip DSC controller)
LCM (MAIN)
LCM (SUB)
IDE/Memory Bus
Mobile Phone or PDA Host
3.2 Host Interface
Host Interface IDE * High speed parallel bus (8-bit or 16-bit) * Ideal attachable CF camera solution especially for PDA with CF slot * Ideal built-in camera solution Host Interface IDE-1 [A3..A1] [D7..D0]
Host CPU
W99686F
RD# WR#
CS#
LCM1
LCM2
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W99686F
Host Interface IDE-2
[A4..A1] [D15..D0] [D15..D0] RD#
Host CPU
RD# WR# CS#
WR#
LCM1
W99686F
R/S# LCS1#
LCM2
R/S# LCS2#
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Publication Release Date: April 13, 2005 Revision A7
W99686F
USB Interface with PC
Sensor Module
Memory Bus Host CPU W99686F USB
LCM1
LCM2
Data Flash
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W99686F
3.3 Camera Implementation
Preview Mode Features * * * * * * * * * * * * Support raw data preview or JPEG preview Support video preview directly to LCM Support video rotation/flip/mirror Support live color effect and sticker display Support up to 30 fps preview depending on the sensor frame rate Support digital zoom
Snapshot Mode Features Support encoding of different size of images Support image rotation/flip/mirror Support color effect and sticker functions Extension to snapshot (single capture) mode Support up to 10 frames burst snapshot at 1/30 sec interval The encoded pictures are stored in W99686 frame buffer, the host can select the favorite ones for storage.
Burst Snapshot Mode Features
Movie Mode Features * * * * * * * * * * * * * * Support real-time video clip encoding The video clip (dumb video) is stored in W99686 frame buffer, the duration depends on the frame rate and resolution Support up to 4M byte video clip in frame buffer Dumb Video Implementation Motion JPEG Movie Implementation
Playback Mode Features Support still JPEG playback directly to LCD or raw data Support motion JPEG video playback direct to LCD or raw data Support image rotation/flip/mirror Support playback mode digital zoom in for 1.0x~2.0x to raw data or 1.0x~7.999x to LCD at small steps Support playback mode digital zoom out to LCD or raw data at N/M (=[0..255]) Support pan/tilt control for LCD output at zoom in Support JPEG re-sizing and re-encoding
Comic Photo Mode Features Support MxN grids of comic photo Each grid of comic photo can come either from a stored JPEG file or a captured video frame.
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W99686F
4. PIN DESCRIPTION
4.1 W99686F Pin Definition (108 balls, LFBGA Package)
The following signal types are used in these descriptions. I IS B BR BU O A P G # Input pin Input pin with Schmitt trigger Bi-directional input/output pin Bi-directional input/output pin with repeater Bi-directional input/output pin with internal pull-up Output pin Analog input/output pin Power supply pin Ground pin Active low
USB Interface (2 pins)
PIN NAME PIN NUMBER TYPE DESCRIPTION
Data Plus line of differential USB upstream port. DP P6 A Note: provide an external 1.5 K pull-up resistor at DP so the device indicates to the host that it is a full-speed device. Data Minus line of differential USB upstream port.
DM
P7
A
UART Interface (2 pins)
PIN NAME PIN NUMBER TYPE DESCRIPTION
TXD / P3[1] RXD / P3[0]
P10 P9
B B
Serial Transmit Data Port-3 Bit-1 Serial Receive Data Port-3 Bit-0
Sensor or Video Input Interface (14 pins) PIN NAME SVID[9:0] SPCLK SVS SHS SCLK PIN NUMBER A7, B8, M14, A8, B9, A9, A10, B10, A11, B11 B7 F13 A6 E7 TYPE I I B B O DESCRIPTION Sensor or Video Data Input SVID[9:0]. Clock for Sensor or Video Data Input Vertical Sync Input. Programmable polarity. Horizontal Sync Input. Programmable polarity. Clock Output to Sensor
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W99686F
LCD Digital Display Interface (22 pins) & POWER ON SETTING (8 pins) PIN NAME LA0 LCD_CS0# LCD_WR#/ LCD_RD# LDAT [7:0]/ Setting [7:0] LDAT [17:8] PIN NUMBER P13 P12 E10 H13 K14, E13, L14, F14, J14, G13, K13, H14 P14, J13, A13, N14, A14, B14, D14, C14, H10, E14 TYPE O O O O BU DESCRIPTION M-LCD: Address-0, for LCD Controller RS signal (CMD/DAT#) M-LCD: LCD Chip Select 0 enable M-LCD: Write Enable/ M-68 mode data RW# control M-LCD: Read Enable/ M-68 mode data enable Digital Display Output Data 8 bits Power On Setting [7:0]
BU
Digital Display Output Data [17:8 ]bits
SD Interface (6 pins) PIN NAME SD_CLK SD_CMD SD[3:0] PIN NUMBER P2 P1 P5, P4, N2, P3 TYPE O O BU DESCRIPTION HCLK for SD Card CLK Host SD_CMD for SD Card CMD signal Host Data for SD Card signal
Host Interface (24 pins) PIN NAME FA0 FA1 FA2 NC FIORD# FIOWR# FCE2# / LCD_CS# FCE1# FD [15:0] PIN NUMBER C1 D1 D2 G5 E5 D13 E2 F2 A2, A1, N10, B1, B2, N9, B5, A3, H1, K5, H2, G1, G2, N8, N6, H5 TYPE BR BR BR BU BU BR BR BR Address-0 Address-1 Address-2 No define I/O Read Strobe I/O Write Strobe Chip Select Signal - 2 LCD Function Selected Chip Select Signal - 1 Data Bus FD[15:0] DESCRIPTION
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W99686F
GPIO (14 pins) PIN NAME GPIO0/ SD_WP# GPIO1/ LCD_CS1# GPIO2/ VBUS GPIO3/ SCK GPIO4/ SDI/SDA GPIO5/ SDO/SDE GPIO7 NC NC GPIO10 SD_CD# GPIO12 GPIO13 GPIO14 GPIO15 Miscellaneous (4 pins) PIN NAME XIN XOUT RESET TME PIN NUMBER J2 J1 M1 N1 TYPE I O IS I DESCRIPTION Reference frequency input from ext. crystal or a clock source. Oscillator output to a crystal. This pin is left unconnected if an external clock source is employed. Reset In. This pin is active high to reset W99686F chip. Test Mode Enable. Only for test, this pin must be connected to GND for normal operation. PIN NUMBER N5 L2 B6 K10 A5 N11 A4 P11 B4 A12 F1 N4 L13 G14 TYPE BU BU BU BU BU BU BU BU BU BU BU BU DESCRIPTION General Purpose I/O [0] Write protect for SD Card General Purpose I/O [1] M-LCD: LCD Chip Select 1 enable General Purpose I/O [2] 20 mA power supply output General Purpose I/O [3] Serial Interface Clock General Purpose I/O [4] Serial Interface Data Input/ Serial Data Acknowledge General Purpose I/O [5] Serial Interface Data Output / Serial Data Enable General Purpose I/O [7] No define No define General Purpose I/O [10] SD Card Inserted Detect General Purpose I/O [12] General Purpose I/O [13] General Purpose I/O [14] General Purpose I/O [15]
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W99686F
Power and Ground (20 pins) PIN NAME VDDB GND VDDI AVDDP AVSSP USBVDD USBVSS VDDFB PIN NUMBER B13, E1, K2, N13 E6, E9, F10, F5, K9, J10, J5, K6 E8, G10, K8 L1 K1 N7 P8 K7 TYPE P G P P G P G P DESCRIPTION I/O Pad Buffer Power Supply. Provide isolated power to the I/O buffers for improved noise immunity. 2.6V~3.6V Ground. Internal Core Logic Power Supply. 1.8V PLL Power Supply. 1.8V PLL Ground. USB Power Supply. 3.0V~3.6V USB Ground. Embedded FRAME BUFFER Power Supply. 2.6V~3.6V
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Publication Release Date: April 13, 2005 Revision A7
W99686F
4.2 W99686F-108b Pin Assignment - (Top View)
A1 CORNER
1 A B C D E F G H J K FD14 FD12 FA0 FA1 VDDB FA2 FCE2#/ LCD_C S# FIOR D# GND NC FD0 GND FD6 GND VDDFB VDDI (1.8V) GND GND SCLK VDDI (1.8V) GND LCD_ WR# GND VDDI (1.8V) LDAT9 GND GPIO 3/SCK FIOW R# LDAT6 SVS LDAT2 LCD_R D# 2 FD15 FD11 3 FD8 4 GPIO7 NC 5 GPIO 4/SDA FD9 6 SHS GPIO2/ VBUS 7 SVID9 SPCLK 8 SVID6 SVID8 9 SVID4 SVID5 10 SVID3 SVID2 11 SVID1 SVID0 12 GPIO 10/SD _CD# 13 14
LDAT15 LDAT13 VDDB LDAT12 LDAT10 LDAT11 LDAT8 LDAT4 GPIO15 LDAT0
GPIO12 FCE1# FD4 FD7 XOUT AVSSP (GND) FD3 FD5 XIN VDDB
LDAT16 LDAT3 LDAT1 LDAT7
L M N
AVDDP GPIO1/ LCD_C (1.8V) S1# RESET TME SD_ CMD SD1 SD_ CLK GPIO0 GPIO13 /SD_W P# SD0 SD2 SD3 FD1 USBV DD DM FD2 USBV SS FD10 P30 / RXD FD13 P31 / TXD GPIO5/ SDO NC LCD_ CS0#
GPIO14 LDAT5 SVID7 VDDB LDAT14
P
DP
LA0
LDAT17
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W99686F
W99686F 108 Ball Location List
LOCATION/ NUMBER B13/ (1) B6/ (2) E5/ (3) D13/ (4) E2/ (5) F2/ (6) F1/ (7) E6/ (8) H5/ (9) N6/ (10) N8/ (11) G2/ (12) G1/ (13) H2/ (14) K5/ (15) H1/ (16) N5/ (17) E1/ (18) J2/ (19) J1/ (20) E9/ (21) L2/ (22) K1/ (23) L1/ (24) N4/ (25) N1/ (26) M1/ (27) P2/ (28) P1/ (29) P3/ (30) N2/ (31) P4/ (32) P5/ (33) PIN NAME VDDB(2.6V~3.6V) GPIO2 / VBUS FIORD# FIOWR# FCE2# / LCD_CS# FCE1# GPIO12 GND FD0 FD1 FD2 FD3 FD4 FD5 FD6 FD7 GPIO0 / SD_WP# VDDB(2.6V~3.6V) XIN XOUT GND GPIO1 / LCD_CS1# AVSSP(GND) AVDDP(1.8V) GPIO13 TME RESET SD_CLK SD_CMD SD0 SD1 SD2 SD3 LOCATION/ NUMBER F14/ (55) L14/ (56) E13/ (57) K14/ (58) E14/ (59) H10/ (60) C14/ (61) D14/ (62) B14/ (63) A14/ (64) N14/ (65) A13/ (66) J13/ (67) P14/ (68) P13/ (69) A12/ (70) P12/ (71) E10/ (72) H13/ (73) B11/ (74) A11/ (75) B10/ (76) A10/ (77) K6/ (78) A9/ (79) B9/ (80) K8/ (81) A8/ (82) M14/ (83) B8/ (84) A7/ (85) B7/ (86) F13/ (87) PIN NAME LDAT4 / SET4 LDAT5 / SET5 LDAT6 / SET6 LDAT7 / SET7 LDAT8 LDAT9 LDAT10 LDAT11 LDAT12 LDAT13 LDAT14 LDAT15 LDAT16 LDAT17 LA0 GPIO10 / SD_CD# LCD_CS0# LCD_WR# LCD_RD# SVID0 SVID1 SVID2 SVID3 GND SVID4 SVID5 VDDI(1.8V) SVID6 SVID7 SVID8 SVID9 SPCLK SVS
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Publication Release Date: April 13, 2005 Revision A7
W99686F
W99686F 108 Ball Location List, Continued
LOCATION/ NUMBER K2/ (34) F10/ (35) P8/ (36) P6/ (37) P7/ (38) N7/ (39) P9/ (40) P10/ (41) N13/ (42) J10/ (43) E8/ (44) F5/ (45) G5/ (46) J5/ (47) H14/ (48) G10/ (49) L13/ (50) G14/ (51) K13/ (52) G13/ (53) J14/ (54)
PIN NAME VDDB(2.6V~3.6V) GND USBVSS DP DM USBVDD P30 / RXD P31 / TXD VDDB(2.6V~3.6V) GND VDDI(1.8V) GND NC GND LDAT0 / SET0 VDDI(1.8V) GPIO14 GPIO15 LDAT1 / SET1 LDAT2 / SET2 LDAT3 / SET3
LOCATION/ NUMBER A6/ (88) E7/ (89) K10/ (90) A5/ (91) N11/ (92) A4/ (93) P11/ (94) B4/ (95) A3/ (96) B5/ (97) N9/ (98) B2/ (99) B1/ (100) N10/ (101) A1/ (102) A2/ (103) C1/ (104) D1/ (105) D2/ (106) K9/ (107) K7/ (108)
PIN NAME SHS SCLK SCK / GPIO3 SDA / GPIO4 SDO / GPIO5 GPIO7 NC NC FD8 FD9 FD10 FD11 FD12 FD13 FD14 FD15 FA0 FA1 FA2 GND VDDFB(2.6V~3.6V)
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W99686F
5. ELECTRICAL CHARACTERISTICS
5.1 Absolute Maximum Ratings
PARAMETER Ambient temperature Storage temperature DC supply voltage for core (1.8V) VDDI DC supply voltage for I/O (2.8V) VDDB I/O pin voltage with respect to VSS
Table 5-1 Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
MIN. -20 -40 0 0 - 0.3
MAX. 70 125 2.0 3.6 VDDB +0.4
UNIT C C V V V
5.2 DC Characteristics
SYMBOL VDDB AVDDP VDDI VIL VIH VOL VOH VOH (P30/P31) IIL IIH IUP IPD PARAMETER Power Supply for I/O Pads Power Supply for PLL Analog Power Supply for Core Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output High Voltage (Open Drain with Internal Pull-Up) Input Low Leakage Current Input High Leakage Current Pull-up Current Power Down Current (XIN=0, No Load) IOUT = -2 mA VIN = 0.4V VIN = 2.4V VIN = 0V Core VDDI= 1.8V I/O VDDB= 2.8V 160x120 preview at 15 fps CPU clock at 12 MHz Engine clock at 24 MHz
Table 5-2
CONDITIONS
MIN. 2.6 1.70 1.70 0 2.0
TYP. 2.8 1.8 1.8
MAX. 3.6 1.90 1.90 0.8 VDDB VSS +0.4
UNIT V V V V V V V
IOUT = 2 mA IOUT = -2 mA VDDB* 0.8
2.0 10 -10 -500 20 120
V A A A A
IDD
Active Current
20
30
mA
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Publication Release Date: April 13, 2005 Revision A7
W99686F
5.2.1 RESET AC Characteristics
RSTI TRST
Figure 5.1
RESET Timing Diagram
RESET Timing SYMBOL TRST PARAMETER Reset Pulse Width
Table 5-3
CONDITIONS
MIN. 1.0
MAX.
UNIT mS
5.2.2
Video Input AC Characteristics
TSPCLK SPCLK THIGH TLOW TSU SVID[7:0] SHS, SVS
1.5 V input valid 1.5 V
TH
1.5 V
Figure 5.2
Input Video Timing Diagram
Input Video Timing SYMBOL FSPCLK THIGH TLOW TSU TH PARAMETER SPCLK Frequency = 1 / TSPCLK SPCLK Clock High Time SPCLK Clock Low Time SVID[9:0], SHS, SVS Setup Time SVID[9:0], SHS, SVS Hold Time
Table 5-4
CONDITIONS
MIN. 5 5 5 6 4
MAX. 48
UNIT MHz nS nS nS nS
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W99686F
5.2.3 Host Interface: CF-IDE Slave (Memory Bus) AC Characteristics
FCE1_,FCE2_ FA2:0]
TCAS TRD TCAH
FIORD#
TODD TODH Valid Data TCAS TWR TCAH
FD[15:0]
FIOWR#
TWDS TWDH
FD[15:0]
Valid Data
Figure 5.3
Host Interface: CF-IDE Slave (Memory Bus) Timing Diagram
Host Interface: CF_IDE Slave (Memory Bus) Timing SYMBOL TCAS TCAH TODD TODH TRD TWDS TWDH TWR PARAMETER Chip Select & Address Set-up Time Chip Select & Address Hold Time FIORD# Low to Data Valid Delay Read Data Output Hold Time FIORD# Pulse Width Write Data Input Setup Time Write Data Input Hold Time WR# Pulse Width
Table 5-5
CONDITION S
MIN. 65 5 --0 *165/4TMCLK 60 2 *165/4TMCLK
MAX. ----2TMCLK -----------
UNIT nS nS nS nS nS nS nS nS
165/4TMCLK : 165ns or 4 internal engine clock cycles
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W99686F
5.2.4 LCD Interface AC Characteristics
LCS_
TLAS TLAH
LA0
TLCSS TLWR TLCSH
80 Mode : LWR#
TLDOD TLDOH Valid Data TLE
LDATA[15:0]
68 Mode : LE
Figure 5.4
LCD Interface Timing Diagram
LCD Interface Timing SYMBOL TLCSS TLCSH TLAS TLAH TLDOD TLDOH TLWR TLE PARAMETER Chip Select Set-up Time Chip Select Hold Time Address Set-up Time Address Hold Time Write Data Active Delay Write Data Hold Time LWR# Pulse Width LE Pulse Width 80 Mode 68 Mode
Table 5-6
CONDITIONS
MIN. 0.5 0.5 1 1 5 0.5 0.5 0.5
MAX. -------------
UNIT PCLK PCLK PCLK PCLK nS PCLK PCLK PCLK
Note: PCLK => Engine Clock / 32
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W99686F
6. PACKAGE DIMENSION
108L LFBGA (8x8 mm, Ball pitch: 0.5 mm, O = 0.3 mm)
E2
E
e
e D2
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Publication Release Date: April 13, 2005 Revision A7
W99686F
7. REVISION HISTORY
VERSION A1 A2 A3 A4 DATE Dec. 18, 2003 Feb. 4, 2004 Feb. 10, 2004 Apr. 23, 2004 PAGE 12 12 11 10 17 A5 A6 A7 Dec. 15, 2004 Feb. 24, 2005 April 13, 2005 18 2, 3, 9, 13 17 Initial Issue Revised GPIO7 & NC pin definition Deleted GPIO9 Revise LDAT [7:0]/ Setting [7:0] pin number definition. Revise TXD/RXD to Bi-directional input/output pin Define VOH to VDDB* 0.8, VOH P30/P31 to Open Drain with Internal Pull-Up / 2.0V. Revise Fspclk to 48Mhz Update USBVDD, LCD I/F. Update IPD DESCRIPTION
Important Notice
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Headquarters
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Winbond Electronics Corporation America
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Winbond Electronics (Shanghai) Ltd.
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9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
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Winbond Electronics (H.K.) Ltd.
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Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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